1. Field of the Invention
The present invention relates to a semiconductor device improved in operation speed by virtue of stress application, and a method of manufacturing the same.
2. Description of the Related Art
In recent LSI, such as those generally called 90-nm-node devices or thereafter, further micronization has been demanded, making transistor performances more difficult to improve. This may be ascribable to that shortening of the gate length increases stand-by, off-state leakage current, and that any attempt of suppressing the off-state leakage current down to a certain level makes current drivability very difficult to improve. For this reason, a new approach of improving transistor performances has been explored.
One of these attempts is known by strained silicon technique. This is a technique of improving current drivability by modifying band structure through application of stress to the channel region, so as to reduce effective mass of carriers to thereby improve carrier mobility.
For n-channel MOS transistors, it has been known that the carrier mobility may be improved by applying uni-axial tensile stress in the direction of channel length of the channel region. As specific examples of applying tensile stress to the channel region, there are proposed a transistor having a film for applying tensile stress formed on the source/drain region of a silicon substrate, and a transistor having a SiC layer filled up in the source/drain region of a silicon substrate, for the purpose of further reliably applying the tensile stress.
An exemplary configuration of the SiC layer filled up in the source/drain region of an n-channel MOS transistor is shown in FIG. 21. In this case, a SiC layer 104 is formed as being buried in a source/drain region 103, on both sides of a gate electrode 101 having sidewalls 102 on both side faces thereof.
Directional sensitivity of stress applied to the channel region of an n-channel MOS transistor and a p-channel MOS transistor, aiming at improving transistor characteristics, is shown in FIG. 22B. Now as listed in FIG. 22A, strain in the direction of channel length of the channel region is given as εxx, strain in the direction perpendicular to the channel region is given as εyy, and strain in the direction of the channel width is given as εzz.
The directional sensitivity of stress aimed at improving transistor characteristics of n-channel MOS transistor may preferably lie in the direction of stretching for εxx, in the direction of compression for εyy, and in the direction of stretching for εzz. However, as shown in FIG. 21, SiC is smaller than Si in the lattice constant, so that any attempt of matching the in-plane lattice thereof to Si as a mother crystal may result in application of planar stress (indicated by arrow A) to the adjacent Si, due to shrinking tendency of the SiC layer 104 per se. As a consequence, in an actual transistor structure, it is understood that the channel region is always applied with compressive stress in the direction of channel width (indicated by arrow B).
In addition, in a transistor structure having a narrow channel region, an element isolation structure, for example, STI element isolation structure, will exert larger influences, and will further increase the compressive stress ascribable to the SiC layer 104 in the direction of channel width of the channel region. FIG. 23 is a characteristic drawing showing strain in the direction of channel width, assuming an origin at the center portion of the channel region. It is understood that the compressive strain in the direction of channel width sharply increases as the position comes closer to the element isolation structure. For this reason, the transistor characteristics of the n-channel MOS transistor with narrow channel width may further be degraded.
In addition, the n-channel MOS transistor shown in FIG. 21 is not understood as being sufficient in terms of compressive strain in the direction perpendicular to the channel region, and is still in need of an effort of further increasing the compressive strain.
For further improvement in the transistor characteristics, it may be also necessary to improve stress of the semiconductor layer, for example the SiC layer, to be filled up in the source/drain region. However, the SiC layer in particular has a stable amount of introduction of C of only as very small as 2% to 3%, and is poor in thermal stability, so that it is difficult to improve the transistor characteristics by further increasing the amount of introduction of C.
In contrast, aiming at improving transistor characteristics of p-channel MOS transistor, Patent Document 3 discloses a configuration in which a SiGe layer is formed as being filled up in the source/drain region, and a tensile stress film is formed on the substrate so as to cover the gate electrode and the sidewall. However, strain action of the SiGe layer and the element isolation structure in the direction of channel width exerted to the channel region of the p-channel MOS transistor is different from that in the n-channel MOS transistor. It is therefore difficult to solve the above-described problems of n-channel MOS transistor by the configuration described in Patent Document 3, even if the constituents in Patent Document 3 should appropriately be replaced by those for n-channel MOS transistor.
The present invention was conceived after considering the above-described problems, and an object thereof is to provide a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate and carrier mobility, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same.